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The Physical Design Engineer will implement and optimize ASIC/SoC physical design flows, including place-and-route, clock tree synthesis, timing analysis, and sign-off checks (DRC/LVS). You will work with RTL and backend teams to meet timing, area, and power targets, ensuring robust silicon tapeouts. The role involves scripting and automation to improve EDA workflows and improve design flows across multiple projects. A strong foundation in ASIC physical design methodologies and CAD tools is required, with collaboration across cross-functional teams.