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Join Qualcomm as an RTL-Synthesis CAD Engineer responsible for building and maintaining RTL synthesis flows and toolchains for digital SoC design. You will optimize RTL and constraints, automate synthesis tasks with Python/Tcl, and support timing closure to improve silicon quality. Collaborate with RTL designers and back-end teams to identify bottlenecks and implement scalable solutions. This role requires strong scripting and digital design knowledge with experience in EDA tooling for synthesis optimization.